1. Field of the Invention
The present invention generally relates to image processing apparatuses, and more particularly to an image processing apparatus that performs image processing operations such as enlarging, reducing and rotating an image when displaying a video data which is stored in a video memory.
2. Related Art
When displaying an image information which is supplied from an image pickup device or the like after subjecting the video information to an image processing such as enlarging, reducing, rotating and scrolling, the video information is first supplied to an independent image processing circuit for making one kind of image processing. The processed video information is then displayed on a cathode ray tube (CRT), for example.
FIG. 1 shows an essential part of a conventional image processing apparatus for explaining an image processing. It will be assumed for the sake of convenience that the video information is to be rotated by the image processing. In FIG. 1, an A-address generating circuit 2 supplies an address signal to an A-video memory 3 and an B-address generating circuit 4 in response to a signal which is received from a bus 1 of a central processing unit (CPU, not shown). The A-video memory 3 stores video information which is received from an image pickup device (not shown) depending on the address signal from the A-address generating circuit 2. The B-address generating circuit 4 carries out multiplication and addition described by the following set of formulas (1) based on the address signal from the A-address generating circuit 2, and supplies to a B-video memory 5 an address signal indicating a coordinate value of the rotated video information: EQU X=cos.theta..multidot.x.sub.o -sin.theta..multidot.y.sub.o Y=sin.theta..multidot.x.sub.o +cos.theta..multidot.y.sub.o( 1)
where x.sub.o and y.sub.o respectively denote address values output from the A-address generating circuit 2, and X and Y respectively denote address values output from the B-address generating circuit 4.
The B-video memory 5 stores the video information from the A-video memory 3 depending on the address signal which is received from the B-address generating circuit 4. The video information stored in the B-video memory 5 is supplied to a display device 6 which is provided with a CRT, for example.
Therefore, the video information from the image pickup device is temporarily stored in the A-video memory 3, and the B-video memory 5 stores the video information depending on the address signal from the B-address generating circuit 4 so that a rotated image can be displayed on the display device 6. In other words, by making a raster scan in which the stored video information is read out from the B-video memory 5 in a sequence of the address, and a display screen of the display device 6 is scanned horizontally in synchronism with the read out operation, an image which is rotated from the original image is displayed on the display device 6.
When performing image processing operations such as enlarging, reducing and rotating on conventional image processing apparatus, two video memories are required. That is, in the above-described case, the A-video memory 3 for storing the image information from the image pickup device, and the B-video memory 5 for storing the processed image information, which is obtained by processing the video information stored in the A-video memory 3, are required for the rotating process. For this reason, there is the problem that it takes a relatively long time to display the processed video information and so that the video information cannot be processed in real time.
In addition, when making the rotating process, the B-address generating circuit 4 requires a multiplier for carrying out the operation described by the set of formulas (1). This means that a high-speed operation circuit having an extremely large scale must be provided to carry out the operation in the B-address generating circuit 4. As a result, the image processing apparatus becomes quite expensive.